Quadrature Encoder-Decoder on a CPLD

Posted 22 Oct 2004 at 22:11 UTC by steve Share This

Electronic Design Magazine has published a quarature encoder-decoder design that can be implemented on any CPLD or FPGA chip. The sample design includes a schematic diagram and VHDL source code for use with a Xilinx CPLD. While it might not be the least expensive way to do it, using a CPLD is an interesting option if you have the hardware available.

Alternatives..., posted 25 Oct 2004 at 15:14 UTC by onnimikki » (Master)

Implementation in a CPLD is certainly interesting. That said, here are some alternatives for people who are interested:

  • HCTL by Agilent
  • The TPU modules on the 68332, MPC555 and MPC5554. These are multi-purpose processors that run in parallel to the main processors. The '5554, which will be released in a few months, has the "enhanced TPU" which can be programmed in C. More info on the TPU and eTPU can be found here.</ li>

Anyone else have suggestions for good quad decoders?

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